1. Field of the Invention
This invention relates to an electronic circuit architecture, and more particularly to a voltage level transfer with a single-end input signal controlled by a gate voltage.
2. Description of Related Art
As the semiconductor fabrication technology achieves to deep sub-micron level, and an IC device with less power consumption is more strongly desired, an internal IC working voltage has been brought down from 5V at the early stage down to 3.3V, 2.5V, or even 1.8V for the current stage. For all of these various IC devices, they should satisfy a standard bus specification so that an external IC voltage level is maintained a standard voltage level, and cannot vary as the internal IC working voltage.
FIG. 1 is a typical circuit diagram, schematically illustrating a signal transmission between two IC devices. In FIG. 1, two IC devices 110, 120 have a common data bus with a standard voltage V.sub.pp of, for example, 3.3V for a signal transmitting between each other through a signal line 130, but they may have different internal IC working voltages. For example, the IC device 110 has a core circuit 115 with an internal working voltage V.sub.dd1 of 3.3V, 2.5V or even as low as 1.8V. Similarly, the IC device 120 has a core circuit 125 with an internal working voltage V.sub.dd2 of 3.3V, 2.5V or even as low as 1.8V. Since the core circuits 115, 125 have different internal working voltage from the standard bus voltage V.sub.pp, they respectively employ a voltage level transfer 116 and a voltage level transfer 126 so as to match the standard bus voltage V.sub.pp carried by the signal line 130.
FIG. 2A is a circuit configuration, schematically illustrating a conventional circuit architecture of a differential-input voltage level transfer. In FIG. 2A, a conventional voltage level transfer 200 includes an inverter 230 and several complementary metal-oxide semiconductor (CMOS) transistors 211, 212, 221, and 222. An input signal Vi is sent in and inverted by the inverter 230 to obtain a complementary input signal Vi, which is continuously sent to the transistor 222 at its gate, and the input signal Vi is simultaneously sent to the transistor 221 at its gate. So, a sub-circuit 240 has Vi and Vi differential-input signals. In this manner, one and only one of the transistors 221 and 222 is turned on at a time. The transistors 211 and 212 are respectively coupled to the transistors 222 and 221 so as to have a positive feedback structure. The positive feed back structure can raise a voltage of the input signal Vi or its complementary input signal Vi so that one of an output signal Vo and its complementary output signal Vo is obtained with a higher voltage level.
FIG. 2B is a plot of voltage waveforms, schematically illustrating voltage waveforms of the input signal Vi and the complementary output signal Vo versus time. In FIG. 2B, at a time t1, the input signal Vi has a voltage level of V.sub.dd, and the complementary output signal Vo has a voltage of 0V. As a result, the transistor 221 is turned on and the transistor 222 is turned off. The voltage level transfer 200 has a design that the driving ability of the transistors 221 and 222 is higher than the driving ability of the transistors 211 and 212 so that as the transistor 221 is turned on, the complementary output signal Vo stays at 0V, which consequently turned on the transistor 212. As a result, the transistor 211 stays "off". Since the transistor 222 is turned off and the transistor 212 is turned on, the output voltage Vo is at the voltage level of V.sub.pp.
As the voltage status of the input signal Vi transits from V.sub.dd to 0V, its complementary input signal Vi has a voltage of V.sub.dd. During voltage transition period, the transistor 211 is not turned on yet at the beginning, but the transistor 221 is turn off and the complementary output signal Vo still stays at 0V. As time going, the transistor 222 is gradually turned on, and the transistor 211 is consequently turned on. Since the complementary output signal Vo controls the transistor 212 at its gate, the transistor still at `on` status. As a result, at this instant time, both the transistor 222 and the transistor 212 are at "on" status, in which they are coupled in series. Because the driving ability of the transistor 222 is greater than the driving ability of the transistor 212, the voltage V.sub.ds of the transistor 222 is greater than the voltage V.sub.sd of the transistor 212. This causes that the voltage of the output signal Vo begins to decrease from a V.sub.pp, and the transistor 211 is gradually turned on. The voltage of the complementary output signal Vo therefore begins to decrease, and the transistor 212 is gradually turned off. This causes the voltage of the output signal Vo to be more easily decreased. As this positive feedback circulation goes on, the output signal Vo obtains a voltage of 0V, and its complementary output signal Vo obtains a stable voltage of V.sub.pp at the time t2.
The conventional voltage level transfer 200 can modify the voltage level carried by the input signal so that the internal working voltage used by the core circuits 115 and 125 of FIG. 1 can match to the standard bus voltage. During the voltage transition period, the transistor 211 and the transistor 221, or the transistor 212 and the transistor 222, are turned on at the same time. The output signal Vo or its complementary output signal Vo with the desired voltage level are done by making use of the higher driving ability of the transistor 221, or the transistor 222. However, since the transistor 211 and the transistor 221, or the transistor 212 and the transistor 222, are coupled in series between the power source V.sub.pp and the ground, and are turned on at the same time, it takes long to transfer the voltage level form internal level to the standard bus level due to a slow response time. This causes an obvious effect of power consumption of a whole IC device, which usually includes several IC devices. This power consumption is a conventional issue which should be solved.